Micom_Electric/마이컴_원칩
2010. 10. 21. 14:27
V1 PA0 VSS SLIDER_1 (2.5 5) ; Amplitude
VMLAB_SIGNALS.txt
V2 PA1 VSS SLIDER_2 (2.5 5) ; Frequency
V1 PB5 VSS SIN(2.5 2.5 2K)
V1 PA0 VSS SLIDER_1(0 5)
V1 PB0 VSS SIN(2.5 2.5 10K)
V2 PB1 VSS SIN(2.5 2.5 11K)
Vin nin VSS SLIDER_1(0 3) ; Slider 1 in Control Panel
V PA5 VSS SLIDER_1(0 5)
Vth minus vss SLIDER_1(0 5) ; Slider controlled source between 0 and 5V
Va2d pb1 vss SLIDER_2(0 5);
K1 PB7 VSS LATCHED ; key + pullup setup
R4 l_node key_node 100
R1 VDD AREF 1
R1 PB7 VDD 10K ; Direction
Rref1 VDD AREF 1K ; Analog reference for
Rref2 AREF VSS 100K ; A/D converer
R4 PD4 PhaseU 10k ; 1st Order RC Filter
R5 PD5 PhaseV 10k
R7 PD7 PhaseW 10k
R8 PhaseU Neutral 100k
R9 PhaseV Neutral 100k
R10 PhaseW Neutral 100k
Rb n1 PB0 47K ; to reproduce PNP transitor behaviour
Rref1 PB2 PB1 1K ; Reference / input resistors
Rref2 PB3 PB1 1K ; stuff. The analog input is
Rin PB1 nin 100K ; INTERACTIVE
R1 PB0 PB1 50K
R2 PB3 fil_out 100K ; PB3 port = OC1 (output compare)
R1 VDD PD3 10K ; pullup resistor
R1 PB2 VSS 1 ; 1 ohm resistor to ground the SSBar signal
R0 VDD PD2 10K
R1 VDD PD3 10K
R VDD PD4 10k
Rpdown TIMER VSS 10K
Ra nand_out PA4 200K
Rb VDD PA4 50K
Rc PA4 VSS 50K
Rpdown TIMER VSS 10K
Ra nand_out PA4 200K
Rb VDD PA4 50K
Rc PA4 VSS 50K
Rt VDD pa7 10K
R1 pa7 n2 680
R2 n2 n3 750
R3 n3 n4 820
R4 n4 n5 1K
R5 n5 n6 1.2K
Rdemo4 n4 VSS 1 ; RS232
R1 pa0 pa1 50K
C1 pa1 vss 200p
C1 fil_out vss 10n
C1 PB1 VSS 10n
c1 PB0 VSS 10n ; of avr401 application note
C4 PhaseU VSS 100n
C5 PhaseV VSS 100n
C7 PhaseW VSS 100n
; LEDS, only 5 LSB
;
D1 VDD PB0
D2 VDD PB1
D3 VDD PB2
D4 VDD PB3
D5 VDD PB4
D1 VDD PD4 ; LED code. Displayed only the 5 LSB
D2 VDD PD3 ; since no more LEDs are available
D3 VDD PD2 ; in the control panel
D4 VDD PD1 ;
D5 VDD PD0 ;
D1 VDD PA3
D2 VDD PA2
D3 VDD PA1
D4 VDD PA0
;kEYS
K0 PD2 vss
K0 PD3 VSS ; Key0 (activated by button 0)
K0 PD2 VSS ; PD2 = INT0, push button 0 to activate it
K1 PD3 VSS ; PD3 = INT1, " " 1 " "
K0 VSS PD4
K0 pb4 VSS
K1 pb3 VSS
K8 key_node vss
K0 pa0 vss latched ; latched, like a radio button
K1 pa1 vss monostable(5m) ; monostable pulse of 5 ms
K2 pa2 vss ; normal key
; Test pattern to trigger breakpoints on rising edges
P NRZ(100u) TRIGGER RESET "00010000100"
; Pattern applied to cancel pin masking the breakpoints
P NRZ(100u) CANCEL RESET "00000000010"
PSendClock NRZ(4u) PB5 KEY_0 "0101010101010101X" ; SCK (clock) is always the
+ KEY_1 "0101010101010101X" ; same pattern, despite
+ KEY_2 "0101010101010101X" ; of the key pressed
+ KEY_3 "0101010101010101X" ;
PSendData NRZ(8u) PB3 KEY_0 "00001111X" ; MOSI (data) gives different
+ KEY_1 "10011000X" ; patterns for each
+ KEY_2 "11110000X" ; key
+ KEY_3 "11001100X" ;
; I2 monitor cells SDA SCL
; Fixed breakpoint time at 200us from simulation start
Xfixed200u _break(200u) VDD GND
; Normal breakpoint on rising edge with no delays
Xnodelay _break(0) TRIGGER GND
X1 _led7cc VDD VDD GND VDD VDD GND VDD GND GND
X2 _led7ca VDD VDD GND VDD VDD GND VDD GND VCC
XletterA11 _led7cc VDD VDD VDD GND VDD VDD VDD GND GND
; The two comxch components that form a virtual null-modem
Xcncb0 _comxch(9600 8 1 0 1) tx0 rx0
Xcncb1 _comxch(9600 8 1 0 1) tx1 rx1
Xone I2C(100K 29) pc4 pc5 ; 100KHz master clock, slave addr = 29 (decimal)
Xtwo I2C( 50K 30) pc4 pc5 ; 50Khz master clock, slave addr = 30 (decimal)
Xnand1 ND2 key_node pa0 n2
Xnand2 ND2 n2 pa2 n3
XOUT _bitctrl PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
XIN _bitdisp PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
X1 _perfmon NC
Xport0 TTY(9600 8 1 0 1) out0 tx0
Xport1 TTY(9600 8 1 0 1) out1 tx1
; Cross-wire and combine port0:TX and cncb1:TX into cncb0:RX
X ND2 out0 tx1 nrx0
X ND2 nrx0 VDD rx0
Xcount0 _vcdlog pd0
Xcount1 _vcdlog pd1
Xcount2 _vcdlog pd2
Xcount3 _vcdlog pd3
; Example delay elements
X _delay(0u 0u) DIN DELAY00
X _delay(3u 3u) DIN DELAY33
X _delay(5u 5u) DIN DELAY55
X _delay(4u 0u) DIN DELAY40
X _delay(0u 4u) DIN DELAY04
Xinput _avrstim(1meg) pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0
Xoutput _avrlog(1meg) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0
; not connect,
; Cross-wire and combine port1:TX and cncb0:TX into cncb1:RX
X ND2 out1 tx0 nrx1
X ND2 nrx1 VDD rx1
; RS R/W E 4 bits interface arbitrary nodes
; --- --- --- ---------------- ---------------
Xdisp LCD(24 2 250K) PD2 PB0 PD3 PD7 PD6 PD5 PD4 nc3 nc2 nc1 nc0
X1 TTY(9600) PD2 PD4
X1 TTY(9600 8) PD0 EXT_RX ;
Xlink1 EXTIN(1) EXT_RX ; TTY Rx from EXTOUT "link1" in Process #2
Xlink2 EXTOUT PD1 ; UART Tx to Process #2 EXTIN "link2"
X1 TTY(9600) PD2 PD4
x1 nd2 PB7 PB7 n1 ; A nand-gate connected as inverter
Xterm TTY(4800 8) PD0 PD1 ; place terminal
; Type in the TX window while the
; simulation is running, after
; the welcome message
Xinv ND2 TIMER TIMER nand_out
Xop opamp plus minus nmi ; Operational amplifier instance
.PLOT V(PD2) V(PD4)