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http://www.edaboard.com/thread8622.html
http://www.edaboard.com/thread175074.html
system -> set simulator options
timestep too small spice
"timestep too small"-- Transient Convergence Problem:
Solution:
0. Check circuit topology and connectivity.
This item is the same as item 0 in the DC analysis.
1. Set RELTOL=.01 in the .OPTIONS statement.
Example: .OPTIONS RELTOL=.01
2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
Example: . OPTION ABSTOL=1N VNTOL=1M
3. Set ITL4=500 in the .OPTIONS statement.
Example: .OPTIONS ITL4=500
4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
5. Reduce the rise/fall times of the PULSE sources.
Example: VCC 1 0 PULSE 0 1 0 0 0
becomes VCC 1 0 PULSE 0 1 0 1U 1U
6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
Example: .OPTIONS RAMPTIME=10NS
7. Add UIC (Use Initial Conditions) to the .TRAN line.
Example: .TRAN .1N 100N UIC
8. Change the integration method to Gear (See also Special Cases below).
Example: .OPTIONS METHOD=GEAR
Regards,
