Micom_Electric/전기전자 2011. 9. 1. 22:36
Logic level ?? 
 
VDS에 따른 Id(A) 량 : 낮은 전압에서 많은 전류가 흐를수 있는것
        따라서 로직레벨이면 5V 이하에서 가능한 많은 전류가 흐른다


http://www.electro-tech-online.com/general-electronics-chat/91756-logic-level-vs-normal-mosfets.html

THe advantage of logic level MOSFETs is that their source-drain saturates with at a low gate voltage. THe disadvantages are that they tend to have higher gate capacitance/gate charge (take longer to turn on for a given amount of drive current), have higher on-resistance, have lower maximum tolerable gate voltages, and cannot be made to have source-drain breakdown voltages as high as standard MOSFETs. You are basically trading the advantage of lower gate drive voltage for performance hits in every other area to varying degrees. Sometimes though the ability to use a logic-level gate voltage simplifies things enough to justify this.

Basically, if you can easily provide the gate voltage necessary for a standard level MOSFET choose a standard MOSFET over a logic level MOSFET (all things being equal). If you cannot provide such a voltage easily, then you have to start thinking about the complexity and performance tradeoffs of supplying that gate drive voltage or using a logic-level FET.



Principle to operate
P-Ch MOSFET : 소자 선택시 VGS 에 주의 Supply - Gate 간 허용 전압임 !


  N-CH MOSFET : VGS에 덜 민감 - ON 상태일 경우 D - S 간 전압이 낮다
                          (S=GND 경우가 대부분)

 

N-CH & P-CH

 
posted by 털보네i

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