Gerber Merge Setup & example - Eagle Panelizing / tiling

이글캐드에서 하는 방법

1. 먼저 이글캐드에서 보드 화일만 오픈
2. run 에서 모든 레이어 표시한 후 penelize.ulp 실행
3. 보드 복사...후 붙여넣기

다른 방법 : Gerbmerge 사용
필요한것
http://ruggedcircuits.com/gerbmerge/
http://www.python.org/  ---> http://www.python.org/ftp/python/2.7.2/python-2.7.2.msi
http://simpleparse.sourceforge.net/ -- 윈도우용 설치
거버 뷰어 http://gerbv.sourceforge.net/

준비
아래 폴더에 모든 거버화일을 모아 놓은 후
주의: eagleCAD용 : http://witt.michael.googlepages.com/gerb274x-m.cam
C:\Python27\gerbmerge
배치 화일 gerbmerge.bat의 경로 확인및 수정
cfg 화일 내용 확인및 수정
*.def 화일에 보드 배치 수정

 
gerbmerge file.cfg file.def <------- 이경우 .def를 따라 수동으로 배치

gerbmerge.bat

lo1.cfg

lo1.def

=============== 참고 def 화일 세팅 =========

Row {
  Col {
    mcu-rev0c
    mcu-rev0c
    mcu-rev0c
  }
...
  Col {
    port-rev0c Rotate90
  }
}

 =============== 참고 cfg 내용 =====

# This configuration file demonstrates panelizing a single job.

##############################################################################

# In the [DEFAULT] section you can create global names to save typing the same

# directory name, for example, over and over.

##############################################################################

[DEFAULT]

#   projdir = . ----- 현재 폴더

projdir = . 

# For convenience, this is the base name of the merged output files.

MergeOut = merge1                 <-----------합치기 작업 완료후 저장될 거버화일이름

#ToolList=proj1.drl

#ExcellonDecimals = 4

CutLineLayers = *topsilkscreen,*bottomsilkscreen

CropMarkLayers = *topsilkscreen,*bottomsilkscreen

FabricationDrawingFile = %(mergeout)s.fab

#FabricationDrawingText = %(projdir)s/fabdwg.txt

ExcellonLeadingZeros = 0

OutlineLayerFile = %(mergeout)s.oln

ScoringFile = %(mergeout)s.sco

PanelWidth = 12.6                        <------- PCB업체의 원판 크기

PanelHeight = 7.8

LeftMargin   = 0.1

RightMargin  = 0.1

TopMargin    = 0.1

BottomMargin = 0.1

XSpacing = 0.125

YSpacing = 0.125

CutLineWidth = 0.01

CropMarkWidth = 0.01

AllowMissingLayers = 0

DrillClusterTolerance = 0.002

[MergeOutputFiles]

Prefix = %(mergeout)s

*TopLayer=%(prefix)s.cmp

*BottomLayer=%(prefix)s.sol

*TopSilkscreen=%(prefix)s.plc

*BottomSilkscreen=%(prefix)s.pls

*TopSoldermask=%(prefix)s.stc

*BottomSoldermask=%(prefix)s.sts

Drills=%(prefix)s.xln

BoardOutline=%(prefix)s.bor

ToolList = toollist.%(prefix)s.drl

Placement = placement.%(prefix)s.txt

##############################################################################

[OBDCANLCD_X010]                                           <----------- 거버화일이름

Prefix=%(projdir)s/OBDCANLCD_X010                    <----------- 거버화일이름

*TopLayer=%(prefix)s.cmp

*BottomLayer=%(prefix)s.sol

*TopSilkscreen=%(prefix)s.plc

*BottomSilkscreen=%(prefix)s.pls

*TopSoldermask=%(prefix)s.stc

*BottomSoldermask=%(prefix)s.sts

Drills=%(prefix)s.xln

BoardOutline=%(prefix)s.bor

#ToolList=proj1.drl

#ExcellonDecimals = 3

#Repeat = 5 

http://arduino.cc/forum/index.php?action=profile;u=19810;sa=showPosts
=== 이하 : 자동일 경우 예제 : 두장의 PCB화일을 자동으로 합치는 예 =======
projdir = .
MergeOut = merge1
[Options]

#ToolList=proj1.drl
#ExcellonDecimals = 4
CutLineLayers = *topsilkscreen,*bottomsilkscreen
CropMarkLayers = *topsilkscreen,*bottomsilkscreen
FabricationDrawingFile = %(mergeout)s.fab
#FabricationDrawingText = %(projdir)s/fabdwg.txt
ExcellonLeadingZeros = 0
OutlineLayerFile = %(mergeout)s.oln
ScoringFile = %(mergeout)s.sco
# panel size here:
PanelWidth = 14.5
PanelHeight = 10
LeftMargin   = 0.1
RightMargin  = 0.1
TopMargin    = 0.1
BottomMargin = 0.1
XSpacing = 0.125
YSpacing = 0.125
CutLineWidth = 0.01
CropMarkWidth = 0.01
AllowMissingLayers = 0
DrillClusterTolerance = 0.002
MinimumFeatureSize = *topsilkscreen,0.008,*bottomsilkscreen,0.008
[MergeOutputFiles]
Prefix = %(mergeout)s
*TopLayer=%(prefix)s.cmp
*BottomLayer=%(prefix)s.sol
*TopSilkscreen=%(prefix)s.plc
*BottomSilkscreen=%(prefix)s.pls
*TopSoldermask=%(prefix)s.stc
*BottomSoldermask=%(prefix)s.sts
Drills=%(prefix)s.xln
BoardOutline=%(prefix)s.bor
ToolList = toollist.%(prefix)s.drl
Placement = placement.%(prefix)s.txt
# options below here are for each PCB in your design
# this is for PCB 1
[pcb1]
Prefix=%(projdir)s/pcb1

*TopLayer=%(prefix)s.cmp
*BottomLayer=%(prefix)s.sol
*TopSilkscreen=%(prefix)s.plc
*BottomSilkscreen=%(prefix)s.pls
*TopSoldermask=%(prefix)s.stc
*BottomSoldermask=%(prefix)s.sts
Drills=%(prefix)s.drd
BoardOutline=%(prefix)s.bor
Repeat = 3

# this is for PCB 2
[pcb2]
Prefix=%(projdir)s/pcb2

*TopLayer=%(prefix)s.cmp
*BottomLayer=%(prefix)s.sol
*TopSilkscreen=%(prefix)s.plc
*BottomSilkscreen=%(prefix)s.pls
*TopSoldermask=%(prefix)s.stc
*BottomSoldermask=%(prefix)s.sts
Drills=%(prefix)s.drd
BoardOutline=%(prefix)s.bor
Repeat = 3